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| \ CDB5460A CDB5460A Evaluation Board and Software Features l Direct General Description The CDB5460A is an inexpensive tool designed to evaluate the functionality and performance of the CS5460A. The CS5460A Data Sheet is supplied in conjunction with the CDB5460A evaluation board. The evaluation board includes an LT1019 voltage reference, an 80C51 microcontroller, an RS232 transceiver, and firmware. The 8051 controls the serial communication between the evaluation board and the PC via the firmware, enabling quick and easy access to all of the CS5460A's registers and functions. The CDB5460A includes software for Data Capture, Time Domain Analysis, Histogram Analysis, and Frequency Domain Analysis. Shunt Sensor and Current Transformer Interface l RS-232 Serial Communication with PC l On-board 80C51 Microcontroller l On-board Voltage Reference l Lab Windows/CVITM Evaluation Software Register Setup & Chip Control FFT Analysis Time Domain Analysis Noise Histogram Analysis l On-board Data SRAM l Integrated RS-232 Test Mode l "Auto-Boot" Demo with serial EEPROM ORDERING INFORMATION CDB5460A Evaluation Board VA+ VACRYSTAL 4.096 MHz AGND VD+ TEST SWITCHES Vu+ CRYSTAL 20.0 MHz RESET CIRCUITRY SERIAL EEPROM VIN+ CS SDI SDO IIN+ SCLK INT EDIR IINEOUT VREF IN OUT REF AGND VOLTAGE REFERENCE 32k x 8 SRAM RS232 CONNECTOR LEDs 80C51 Microcontroller VIN- CS5460 RS232 TRANSCEIVER Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved) JUL `00 DS487DB1 1 CDB5460A TABLE OF CONTENTS 1. HARDWARE .......................................................................................................................5 1.1 Introduction .................................................................................................................5 1.2 Evaluation Board Overview .........................................................................................5 1.2.1 Analog Section ..................................................................................................5 1.2.2 Digital Section ...................................................................................................6 1.2.3 Power Supply Section .......................................................................................6 1.3 Using the Evaluation Board ........................................................................................6 2. SOFTWARE ........................................................................................................................8 2.1 Installation Procedure .................................................................................................9 2.2 Using the Software ......................................................................................................9 2.3 Selecting and Testing a COM Port .............................................................................9 2.4 Register Access in the Setup Window ......................................................................10 2.4.1 Refresh Screen Button ....................................................................................10 2.4.2 CS5460A Crystal Frequency ...........................................................................10 2.4.3 Configuration Register .....................................................................................10 2.4.4 Mask Register / Status Register ......................................................................11 2.4.5 Cycle Count / Pulse Rate / Time Base Registers ............................................11 2.4.6 Control Register ..............................................................................................12 2.5 Calibration Window ...................................................................................................12 2.5.1 Offset / Gain Register ......................................................................................12 2.5.2 Performing Calibrations ...................................................................................12 2.6 Conversion Window ..................................................................................................13 2.6.1 Single Conversion Button ................................................................................14 2.6.2 Continuous Conversions Button ......................................................................14 2.6.3 Re-Initialize Serial Port Button ........................................................................14 2.6.4 Standby / Sleep Mode Buttons ........................................................................14 2.6.5 Power Up Button .............................................................................................14 2.7 Viewing Pulse Rate Output Data ..............................................................................14 2.7.1 Integration Period Box .....................................................................................15 2.7.2 Periods To Average Box .................................................................................15 2.7.3 Start Button .....................................................................................................15 2.8 Data Collection Window Overview ............................................................................15 2.8.1 Time Domain / FFT / Histogram Selector ........................................................15 2.8.2 Collect Button ..................................................................................................17 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ IBM, AT and PS/2 are trademarks of International Business Machines Corporation. Windows is a trademark of Microsoft Corporation. Lab Windows and CVI are trademarks of National Instruments. SPITM is a trademark of Motorola. MicrowireTM is a trademark of National Semiconductor. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS487DB1 CDB5460A 2.8.3 Config Button .................................................................................................. 17 2.8.4 Output Button .................................................................................................. 17 2.8.5 Zoom Button .................................................................................................... 17 2.8.6 Channel Select Buttons ................................................................................... 17 2.9 Config Window ......................................................................................................... 17 2.9.1 Number of Samples ........................................................................................ 17 2.9.2 Average ........................................................................................................... 17 2.9.3 FFT Window .................................................................................................... 17 2.9.4 Histogram Bin Width ....................................................................................... 17 2.9.5 Pages to Collect .............................................................................................. 17 2.9.6 Data to Collect ................................................................................................. 17 2.9.7 Accept Button .................................................................................................. 18 2.10 Collecting Data Sets ...............................................................................................18 2.11 Retrieving Saved Data From a File ........................................................................ 18 2.12 Analyzing Data ....................................................................................................... 18 2.13 Histogram Information ............................................................................................ 18 2.13.1 BIN ................................................................................................................ 18 2.13.2 MAGNITUDE ................................................................................................. 18 2.13.3 MAXIMUM ..................................................................................................... 18 2.13.4 MEAN .....................................................................................................................19 2.13.5 MINIMUM ......................................................................................................19 2.13.6 STD. DEV. ..................................................................................................... 19 2.13.7 VARIANCE .................................................................................................... 19 2.14 Frequency Domain Information .............................................................................. 19 2.14.1 FREQUENCY ................................................................................................ 19 2.14.2 MAGNITUDE ................................................................................................. 19 2.14.3 S/D ................................................................................................................ 19 2.14.4 S/N+D ........................................................................................................... 19 2.14.5 SNR ............................................................................................................... 19 2.14.6 S/PN .............................................................................................................. 19 2.14.7 # of AVG ........................................................................................................ 19 2.15 Time Domain Information ....................................................................................... 19 2.15.1 COUNT ......................................................................................................... 19 2.15.2 MAGNITUDE ................................................................................................. 19 2.15.3 MAXIMUM ..................................................................................................... 19 2.15.4 MINIMUM ......................................................................................................19 3. ADDENDUM ..................................................................................................................... 28 3.1 Board Modifications for Charge Pump ...................................................................... 28 LIST OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Start-Up Window ....................................................................................... 10 Setup Window ........................................................................................... 11 Calibration Window ................................................................................... 12 Conversion Window ..................................................................................13 Pulse Rate Output Window ....................................................................... 14 Time Domain Analysis .............................................................................. 15 FFT Analysis ............................................................................................. 16 Histogram Analysis ................................................................................... 16 Analog Schematic Part 1 .......................................................................... 20 Analog Schematic Part 2 .......................................................................... 21 Digital Schematic Part 1 ............................................................................22 DS487DB1 3 CDB5460A Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Digital Schematic Part 2 ............................................................................23 Power Supply Schematic ..........................................................................24 Silkscreen ..................................................................................................25 Circuit Side ................................................................................................26 Solder Side ................................................................................................27 LIST OF TABLES Table 1. Reference Selection .............................................................................................5 Table 2. Power Supply Connections .................................................................................6 Table 3. Header, Jumper, and DIP Switch Descriptions ...................................................7 Table 4. DIP Switch S1 Setting ..........................................................................................8 4 DS487DB1 CDB5460A 1. HARDWARE 1.1 Introduction The CDB5460A evaluation board provides a quick means of evaluating the CS5460A Power Meter IC. The CDB5460A evaluation board's analog section operates from either a single +5 V or dual 2.5 V power supply. The evaluation board interfaces the CS5460A to an IBMTM compatible PC via an RS232 interface. To accomplish this, the board comes equipped with an 80C51 microcontroller and a 9pin RS-232 cable which physically interfaces the evaluation board to the PC. Additionally, analysis software provides easy access to the internal registers of the CS5460A, and provides a means to display the performance in the time domain or frequency domain. put leads. The 3 dB corner of the filter is approximately 50 KHz differential and common mode. The evaluation board provides three voltage reference options, on-chip, on-board and external, as shown in Figure 10. Table 1 illustrates the options available. With HDR4's jumpers in position REFOUT, the on-chip reference provides 2.5 volts. With HDR4's jumpers in position LT1019, the LT1019 provides 2.5 volts (the LT1019 was chosen for its low drift, typically 5 ppm/C). By setting HDR4's jumpers to position REF+, the user can supply an external voltage reference to J2's REF+ and VA- inputs. Application Note 4 on the web (http://www.cirrus.com/products//pubs.html) details various voltage references. Reference LT1019 Description Selects on board LT1019 Reference (5ppm/C) Selects external reference Selects the reference supplied by CS5460A O O O O O O O O O 1.2 Evaluation Board Overview The board is partitioned into two main sections: analog and digital. The analog section consists of the CS5460A and a precision voltage reference. The digital section consists of the 80C51 microcontroller, 32 Kilobytes of SRAM, the hardware test switches, the reset circuitry, and the RS-232 interface. The board also has a user friendly power supply connection. HDR4 O LT1019 O REF+ O REFOUT O LT1019 O REF+ O REFOUT O LT1019 O REF+ O REFOUT REF+ REFOUT 1.2.1 Analog Section The CS5460A is designed to accurately measure and calculate: Energy, Instantaneous Power, IRMS, and VRMS while operating from a 4.096 MHz crystal. As shown in Figure 9 there are four BNC connectors (J9, J10, J11, J12) provided for converter input connections. A Shunt Sensor or Current Transformer can be connected to the converter's current inputs via J10 (IIN+) and J9 (IIN-). A voltage divider can be connected to the converter's voltage input via J12 (VIN+) and (J11) (VIN-). Note, a simple RC network filters the sensor's output to reduce any interference picked up by the in- Table 1. Reference Selection The CS5460A serial interfaces are SPITM and MicrowireTM compatible. The interface control lines (CS, SDI, SDO, and SCLK) are connected to the 80C51 microcontroller via port one. To interface an external microcontroller, these control lines are also connected to HDR6 (Header 6). However to accomplish this, the evaluation board must be modified in one of three ways: 1) cut the interface control traces going to the microcontroller, 2) remove resistors R4, R7, R8, and R13, or 3) remove the microcontroller. DS487DB1 5 CDB5460A 1.2.2 Digital Section The schematics for the digital section are shown in Figures 11 and 12. The digital section contains the microcontroller, test switches, a Motorola MC145407 interface chip, and 32K bytes of SRAM, and one serial EEPROM. The test switches aid in debugging communication problems between the CDB5460A and the PC. The microcontroller derives its clock from a 20.0 MHz crystal. From this, The RS-232 data conversion IC (U1) is configured to communicate via RS-232 at 9600 baud, no parity, 8-bit data, and 1 stop bit. be +5 Volts only. Table 2 shows the various power connections with the required jumper settings on HDR3 and HDR5. 1.3 Using the Evaluation Board The CS5460A is a highly integrated device, containing dual ADCs with a computational unit. The CS5460A and CDB5460A data sheets should be read thoroughly and understood before using the CDB5460A evaluation board. The CS5460A contains a programmable gain amplifier (PGA), two modulators, two high rate filters, an on-chip reference, and power calculation engine to compute Energy, VRMS, IRMS, and Instantaneous Power. The PGA sets the input levels of the current channel at either 30 mVRMS or 150 mVRMS (for VREFIN = 2.5 V). The on-chip reference can provide the necessary 2.5 V reference. This output (VREFOUT) is used to supply the VREFIN pin with 2.5 V. The modulators and high rate digital filter allow the user to measure instantaneous voltage, current, and power at a output word rate of 4000 Hz when a 4.096 MHz clock source is used. Table 3 describes the various headers, jumpers and DIP switches on the CDB5460A evaluation board. DIP switch S1 is used to control the 80C51. Table 4 illustrates the varies setting of the DIP Switch S1. 1.2.3 Power Supply Section Figure 13 illustrates the power supply connections to the evaluation board. The VA+ post supplies the positive analog section of the evaluation board, the LT1019 and the ADC. The VA- post supplies the negative analog voltage circuitry. Note, this terminal is grounded when powering the CDB5460A from a single +5 Volt analog supply. The VD+ post supplies the digital section of the ADC and level shifter. The Vu+ post supplies the digital section of the evaluation board, the 80C51, the reset circuitry, and the RS-232 interface circuitry. Note, the board's digital section supplied via Vu+ post, must Power Supplies Analog Digital +5V +5V VA+ +5 Power Post Connections VAGND VD+ NC GND +5 Jumpers Vu+ NC HDR5 Vu+ O VD+ O VD+ O VA+ O Vu+ O VD+ O VD+ O VA+ O Vu+ O VD+ O VD+ O VA+ O O O O O O O O O O O O O VDDD VDDD D+ D+ VDDD VDDD D+ D+ VDDD VDDD D+ D+ HDR3 VA- O A- O O DGND O DGND +5V +3V +5 NC GND +3 +5 VA- O A- O O DGND O DGND 2.5V +3V +2.5 -2.5 NC +3 +5 VA- O A- O O DGND O DGND Table 2. Power Supply Connections 6 DS487DB1 CDB5460A Name HDR1 Function Description Default Setting Default Jumpers O O O VIN+ O GND Used to switch VIN+ on the CS5460A between J12 VIN+ Set to BNC J12 and GND. Used to switch VIN- on the CS5460A between J11 and GND. VIN- Set to BNC J11 Negative Analog Power Supply Set to 0V VREFIN Set to onchip reference VREFOUT HDR2 O O O VINO GND HDR3 Used to switch VA-, A-, and GND. Refer to Table 2 VA- O A- O O GND O GND HDR4 Used to switch the VREFIN from external J2 header, to the on board LT1019 reference, or to the on-chip reference VREFOUT. Refer to Table 1 O O O O LT1019 O REF+ O REFOUT HDR5 HDR6 HDR7 Used to switch VU+, VD+, and VA+ to VDDD and/or Digital Power Supply D+. Refer to Table 2 Set to +5V Used to connect an external micro-controller. Connected to 80C51 Used in conjunction with the self test modes to test RS-232 Set to Normal the UART/RS-232 communication link between the Mode microcontroller and a PC. Used to switch IIN+ on the CS5460A between J10 and GND. Used to switch IIN- on the CS5460A between J9 and GND. IIN+ Set to BNC J10 Vu+ O VD+ O VD+ O VA+ O O O O O VDDD VDDD D+ D+ NC O O O O HDR7 3 HDR8 O O O IIN+ O GND HDR9 IIN- Set to BNC J11 O O O IINO GND HDR10 Used to switch XIN on the CS5460A to HDR6 when XIN Set for on-board an external micro-controller is used. 4.096 MHz XTAL Used to connect PFMON pin on the CS5460A to monitor Power Supply VA+ Used to connect the RESET Button to the CS5460A DIP switch to control 80C51 S1-1 is used to select RS-232 test mode S1-2 is used to select crystal to 80C51 S1-3 is used to enable auto-boot mode Allows LEDs D3 and D5 to indicate pulses on /EOUT and /EDIR. Pulse frequency must be less than ~6Hz to see light. PFMON Set Monitor VA+ RESET Set not connected to CS5460A S1-1 Set Normal S1-2 Set 20 MHz S1-3 Auto-Boot off Disable LEDs 1 O O O DGND O XIN JP2 JP4 O O JP2 O O JP4 2 S1 OPEN HDR11 O O HDR11 HDR12 Used to disconnect XTAL1 input on microcontroller Use on-board crystal from off-board oscillator input. Table 3. Header, Jumper, and DIP Switch Descriptions O O HDR12 DS487DB1 7 CDB5460A 80C51 Mode 80C51 is in Normal Operating Mode S1-1 OPEN S1-2 CLOSED 20 MHz Crystal S1-3 OPEN 80C51 is in Normal Operation Mode S1-1 OPEN S1-2 OPEN 11.059 MHz Crystal S1-3 OPEN 80C51 is in Test Mode S1-1 CLOSED S1-2 CLOSED 20 MHz Crystal S1-3 OPEN 80C51 is in Test Mode S1-1 CLOSED S1-2 OPEN 11.059 MHz Crystal S1-3 OPEN Auto-Boot Mode S1-1 OPEN S1-2 CLOSED S1-3 CLOSED Table 4. DIP Switch S1 Setting 1 S1 2 3 OPEN CS5460A for continuous conversion mode. If voltage and current signals are applied to the inputs, the CS5460A will issue pulses on the /EOUT and /EDIR pins. Note that JP4 header must be shorted for auto-boot to work. When the CDB5460 Evaluation Board is sent from the factory, the EEPROM is programmed with the following CS5460A command/data sequence: 40 00 00 61 4C 10 00 00 ;In configuration Register, turn highpass filters on, set K = 1. ;Set Pulse Rate Register to 32768 Hz. ;Start continuous conversions. ;Write stop bit to CS5460A to terminate autoboot sequence. 1 2 3 OPEN 1 2 3 OPEN E8 1 2 3 78 00 01 00 OPEN 1 2 3 OPEN The auto-boot sequence runs with no assistance from the 8051 microcontroller. The user can verify this by disconnecting power from the board, pulling the microcontroller out of its socket, then power on again and run in auto-boot mode. See the CS5460A data sheet for more details on auto-boot. The S1-1 switch should be set to the OPEN position for normal operation. When testing the RS-232 link in the PC software, close S1-1. The S1-2 switch selects the crystal source for the 80C51. There are two crystal options available, 11.059 MHz and 20 MHz. If S1-2 is OPEN the 11.059 MHz crystal is selected, and when S1-2 is CLOSED the 20 MHz crystal is selected. If S1-3 is closed, the CS5460A operates in autoboot mode. When in auto-boot mode, a hardware reset (press on S2) will cause the CS5460A to boot up using the serial data from the serial EEPROM on the board (U9). The EEPROM must be programmed prior to the auto-boot sequence. The EEPROM does come pre-programmed with a valid boot-up sequence. This sequence programs the 2. SOFTWARE The evaluation board comes with software and an RS-232 cable to link the evaluation board to the PC. The evaluation software was developed with Lab Windows/CVITM, a software development package from National Instruments. The software was designed to run under Windows 95TM or later, and requires about 3MB of hard drive space (2MB for the CVI Run-Time EngineTM, and 1MB for the evaluation software). After installing the software, read the readme.txt file for any last minute updates or changes. More sophisticated analysis software can be developed by purchasing the development package from National Instruments (512-7940100). 8 DS487DB1 CDB5460A 2.1 Installation Procedure 1) Turn on the PC, running Windows 95TM or later. 2) Insert the Installation Diskette #1 into the PC. 3) Select the Run option from the Start menu. 4) At the prompt, type: A:\SETUP.EXE Notes: The software is written to run with 640 x 480 resolution; however, it will work with 1024 x 768 resolution. If the user interface appears to be small, the user might consider setting the display settings to 640 x 480. (640x480 was chosen to accommodate a variety of computers). When the software is launched, the Start-Up window appears first (Figure 1). This window contains information concerning the software's title, revision number, copyright date, etc. At the top of the screen is a menu bar which displays user options. The menu bar item Menu is initially disabled to prevent conflicts with other serial communications devices, such as the mouse or a modem. After selecting a COM port, the Menu item will become available. 2.3 Selecting and Testing a COM Port Upon start-up, the user is prompted to select the serial communications port which will interface to the CDB5460A board. To select the COM port, pull down the Setup menu option, and select either COM1 or COM2 (the DISK option is used for previously saved files, and is discussed later). Testing the COM port to verify communication between the PC and the evaluation board is not necessary, but can help to troubleshoot some problems. The procedure for testing the communication link follows. 1) Pull down the Setup menu option again, and select TEST RS-232. 2) When prompted, set DIP switch 1 (the leftmost DIP switch) to the closed position, reset the board, and press OK to perform the test. 3) If the test passes, set DIP switch 1 to the open position, and reset the board to return to normal operating mode. 4) If the test fails, check the serial port connections, power connections, jumpers, and DIP switch settings on the board, and run the test again from step 1. Once the serial link is established between the PC and the evaluation board, the user is ready to access the internal registers of the CS5460A, collect data, and perform analysis on the collected data. 2.2 Using the Software Before launching the software, the user should set up the CDB5460A evaluation board by using the correct jumper and DIP switch settings as described in Part I, and connect it to an open COM port on the PC using the RS-232 serial cable. Once the board is powered on, the user can start the software package. DS487DB1 9 CDB5460A Figure 1. Start-Up Window 2.4 Register Access in the Setup Window The Evaluation software provides access to the CS5460A's internal registers in the Setup Window (Figure 2). The user can enter the Setup Window by pulling down Menu and selecting Setup Window, or by pressing F2 on the keyboard. In the Setup Window, all of the CS5460A's registers are displayed in hexadecimal notation, and also decoded to provide easier readability. Refer to the CS5460A data sheet for information on register functionality and meanings. ing any registers to reflect the current status of the part. 2.4.2 CS5460A Crystal Frequency The CS5460A accepts a wide range of crystal input frequencies, and can therefore run at many different sample rates. The crystal frequency being used on the CS5460A should be entered in this box to provide accurate frequency calculations in the FFT window. This will also help the software decide which functions can be performed reliably with the evaluation system. 2.4.1 Refresh Screen Button The Refresh Screen button will update the contents of the screen by reading all the register values from the part. This usually takes a couple of seconds, but it is a good idea to press the Refresh Screen button when entering the Setup Window, or after modify- 2.4.3 Configuration Register In the Configuration Register box, the contents of the Configuration Register can be modified by typing a hexadecimal value in the HEX: box, or by changing any of the values below the HEX: box to the desired settings. Note that when changing the 10 DS487DB1 CDB5460A Figure 2. Setup Window value of the reset bit to `1' (RS, bit 7 in the Configuration Register), the part will be reset, and all registers will return to their default values. Press the Refresh Screen button after performing a reset to update the screen with the new register values. Note: Although the CDB5460A software allows the user to modify any of the bits in the Configuration Register, changing certain bits may cause the software and board to behave erratically. For the evaluation system to function properly, the Interrupt Output function should be set to the default Active Low, and the Eout / Edir Function should be set to the default Normal. This applies only to the CDB5460A evaluation system, and not to the CS5460A chip itself. checking the appropriate check boxes for the bits that are to be masked. The Status Register cannot be directly modified. It can only be reset by pressing the Clear Status Register Button. The HEX: box for this register, and the LEDs are display only. A LED that is on means that the corresponding bit in the Status Register is set (except the Invalid Command bit, which is inverted). Note: The value present in the Mask register may be changed by the software during certain operations to provide correct functionality of the CDB5460A board. 2.4.5 Cycle Count / Pulse Rate / Time Base Registers These three boxes display the values of the Cycle Count, Pulse Rate, and Time Base Registers in both hexadecimal and decimal format. All three registers can be modified by typing a value in the corresponding Value: or HEX: box. 2.4.4 Mask Register / Status Register The Mask and Status Registers are displayed in hexadecimal and decoded in this box to show what each of the bits means. The Mask Register can be modified by typing a value in the HEX: box, or by DS487DB1 11 CDB5460A 2.4.6 Control Register The Control Register contains various bits used to activate or terminate various features of the CS5460A. Refer to the CS5460A data sheet for description of the bits. The user is able to turn each bit on or off individually. The value of the Control Register is displayed in HEX. Note that the Control Register, like all other CS5460A registers, is 24 bits long. Most of these bits are reserved or unused. Only the usable bits are displayed in the Setup Window. CS5460A data sheet for more details on calibration. 2.5.1 Offset / Gain Register In the Offset and Gain Register boxes, the offset and gain registers for both channels are displayed in hexadecimal and decimal. These registers can all be modified directly by typing the desired value in the hexadecimal display boxes. There are two types of offset registers: DC offset and AC offset. The AC offset registers only affect the RMS-register values. Note that the RMS offset registers only hold positive values between 0 and +1. The DC offset register is a two's complement number whose value ranges from -1 to +1. 2.5 Calibration Window The Calibration Window is used to display and write to the CS5460A offset and gain calibration registers. The user is also able to initiate the CS5460A's calibration sequences that are used to set the calibration values. Both AC and DC calibrations can be run for offset and gain, for either the voltage channel or the current channel, or both simultaneously. The user should refer to the 2.5.2 Performing Calibrations Offset and gain calibrations can be performed on both the voltage and current channels of the CS5460A. It is generally a good idea to softwarereset the CS5460A before running calibrations, because the values in the calibration registers will affect the results of the calibration. A software reset Figure 3. Calibration Window 12 DS487DB1 CDB5460A will reset these registers back to the default values of zero offset and unity gain. Offset calibration should be performed before gain calibration to ensure accurate results. HDR8, and HDR9) are set to the input position. 2) Press the corresponding AC or DC gain calibrate button (Cal V, Cal I, or Cal Both) in the Gain Register box. 3) The calibration value(s) will automatically update when the calibration is completed. The Calibration Window also contains the Power Offset Register display and adjustment. The user can read and write the value in the Power Offset Register. 2.5.2.1. Offset Calibrations: 1) Ground the channel(s) you want to calibrate directly at the channel header(s). HDR1 and HDR2 for the voltage channel, and HDR8 and HDR9 for the current channel. The channel(s) could also be grounded directly at the BNC connectors. 2) Press the corresponding AC or DC offset calibrate button (Cal V, Cal I, or Cal Both) in the Offset Register boxes. 3) The calibration value(s) will automatically update when the calibration is completed. 2.6 Conversion Window The Conversion Window (Figure 4) allows the user to see the results of single and continuous conversions on all six data registers, perform data averaging, utilize the power-saving modes of the CS5460A, and reset the CS5460A's serial port. The Conversion Window can be accessed by pulling down the Menu option, and selecting Conversion Window, or by pressing F3. 2.5.2.2. Gain Calibrations: 1) Attach an AC or DC calibration signal to the BNC connector(s), and make sure the corresponding channel headers (HDR1, HDR2, Figure 4. Conversion Window DS487DB1 13 CDB5460A 2.6.1 Single Conversion Button On pressing this button, single conversions will be performed repeatedly until the user presses the Stop button. After each conversion is complete, the Result data column will update with the values present in each data register. The Mean and Standard Deviation columns will update every N cycles, where N is the number in the Samples to Average box. Note that it can take many collection cycles after pressing the Stop button before the data actually stops being collected. CS5460A data sheet to the part. This sequence brings the CS5460A's serial port back to a known state. It does not reset any of the registers in the part. 2.6.4 Standby / Sleep Mode Buttons When these buttons are pressed, the part will enter either Standby or Sleep power saving modes. To return to normal mode, use the Power Up button. 2.6.5 Power Up Button This button is used to send the Power Up/Halt command to the CS5460A. The part will return to normal operating mode and halt any conversions that are being done at this time. 2.6.2 Continuous Conversions Button This button functions similarly to the Single Conversion button, except that continuous conversions are performed instead. The data on the screen is updated in the same fashion, and the Stop button terminates this action. There are some speed limitations when performing this function, and if any of these limitations are exceeded, the user will be prompted to change some settings before proceeding. 2.7 Viewing Pulse Rate Output Data The CS5460A features a pulse-rate energy output. The CDB5460A has the capability to demonstrate the functionality of this output in the Pulse Rate Output Window (Figure 5). The Pulse Rate Output Window can be accessed by pressing the F4 key, or by pulling down the Menu option, and selecting Pulse Rate Window. 2.6.3 Re-Initialize Serial Port Button When this button is pressed, the software will send the synchronization sequence discussed in the Figure 5. Pulse Rate Output Window 14 DS487DB1 CDB5460A 2.7.1 Integration Period Box This box allows the user to select the length of time which pulses will be collected over. limitations of the on-board microcontroller, some higher pulse rates cannot be accurately collected. If the pulse rate is too high, a warning message will appear. 2.7.2 Periods To Average Box This box allows the user to average a number of integration periods together. 2.8 Data Collection Window Overview The Data Collection Window (Figures 6, 7, and 8) allows the user to collect sample sets of data from the CS5460A and analyze them using time domain, FFT, and histogram plots. The Data Collection Window is accessible through the Menu option, or by pressing F5. 2.7.3 Start Button When the Start button is pressed, the CDB5460A will capture pulse rate data according to the values in the Integration Period and Periods to Average boxes. After each integration period, the Pulse Count and Frequency columns will be updated. The Average Freq. and Standard Deviation columns will only be updated after all of the integrations have been collected. The software stops collecting data when the user presses the Stop button, or when the data collection is finished. Due to some speed 2.8.1 Time Domain / FFT / Histogram Selector This menu selects the type of data processing to perform on the collected data and display in the plot area. Refer to the section on Analyzing Data for more information. Figure 6. Time Domain Analysis DS487DB1 15 CDB5460A Figure 7. FFT Analysis Figure 8. Histogram Analysis 16 DS487DB1 CDB5460A 2.8.2 Collect Button This button will collect data from the part, to be analyzed in the plot area. See the section on Collecting Data Sets for more information. memory size on the CDB5460A, the maximum is 4096 samples when collecting two channels, and 2048 samples when collecting three channels. 2.9.2 Average When doing FFT processing, this box will determine the number of FFTs to average. FFTs will be collected and averaged when the Collect button is pressed. 2.8.3 Config Button This button will bring up the configuration window, in which the user can modify the data collection specifications. See the discussion of the Config Window in this document. 2.9.3 FFT Window This box allows the user to select the type of windowing algorithm for FFT processing. Windowing algorithms include the Blackman, Blackman-Harris, Hanning, 5-term Hodie, and 7-term Hodie. The 5-term Hodie and 7-term Hodie are windowing algorithms developed at Crystal Semiconductor. 2.8.4 Output Button This button will bring up a window in which the user can output the data to a file for later use, print out a plot, or print out the entire screen. Note: When saving data, only the data channel being displayed on the plot will be saved to a file. 2.8.5 Zoom Button This button allows the user to zoom in on the plot by selecting two points in the plot area. Press the Restore button to return to the normal data plot, or press the Zoom button again to zoom in even further. 2.9.4 Histogram Bin Width This box allows for a variable "bin width" when plotting histograms of the collected data. Each vertical bar in the histogram plot will contain the number of output codes contained in this box. Increasing this number may allow the user to view histograms with larger input ranges. 2.8.6 Channel Select Buttons Depending on the number of channels of information that has been collected, between 1 and 3 channel select buttons will appear below the graph, allowing the user to choose the appropriate channel for display. In the Time Domain mode, an additional button labeled "Overlay" will be present, to allow the user to display all of the channels on the same plot. 2.9.5 Pages to Collect This box determines the number of data "pages" that the microcontroller will collect before sending data to the PC. Each page consists of the number of samples collected, and only the last page will be returned to the PC for processing. This function is useful at higher sampling frequencies to minimize board-level noise at the beginning of the conversion set. 2.9 Config Window The Config Window allows the user to set up the data collection and analysis parameters. 2.9.6 Data to Collect These six check boxes allow the user to select the data channels that will be collected and returned to the PC for processing. Up to three channels can be selected at once. There are some restrictions on the speed and number of samples to collect when selecting more than one channel. A warning message 17 2.9.1 Number of Samples This box allows the user to select the number of samples to collect, between 16 and 8192. Due to DS487DB1 CDB5460A will appear on pressing the Collect button in the Data Collection Window if any speed limits appear to be exceeded, but the data collection will still take place. 2) Find the data file in the list and select it. Press the Select button to return. 3) Go to the Data Collection Window, and press the Collect button. 4) The data from the file should appear on the screen. To select a different file, repeat the procedure. 2.9.7 Accept Button When this button is pressed, the current settings will be saved, and the user will return to the Data Collection Window. 2.12 Analyzing Data The evaluation software provides three types of analysis tests - Time Domain, Frequency Domain, and Histogram. The Time Domain analysis processes acquired conversions to produce a plot of Magnitude versus Conversion Sample Number. The Frequency Domain analysis processes acquired conversions to produce a magnitude versus frequency plot using the Fast-Fourier transform (results up to Fs/2 are calculated and plotted). Also, statistical noise calculations are calculated and displayed. The Histogram analysis test processes acquired conversions to produce a histogram plot. Statistical noise calculations are also calculated and displayed. 2.10 Collecting Data Sets To collect a sample data set: 1) In the Data Collection Window, press the Config button to bring up the Configuration Window and view the current settings. 2) Select the appropriate settings from the available options (see the section on the Configuration Window) and press the Accept button. 3) The Data Collection Window should still be visible. Press the Collect button to begin collecting data. A progress indicator bar will appear at the bottom of the screen during the data collection process. 4) Data is first collected from the CS5460A and stored in SRAM, and then transferred from the SRAM to the PC through the RS-232 serial cable. Depending on the value of the Cycle Count Register and the number of samples being collected, this process may take a long time. The process can be terminated by pressing the Stop button, but if this is done, the user should also press Reset on the CDB5460A board. 5) Once the data has been collected, it can be analyzed, printed, or saved to disk. 2.13 Histogram Information The following is a description of the indicators associated with Histogram Analysis. Histograms can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to Histogram (Figure 8). 2.13.1 BIN Displays the x-axis value of the cursor on the Histogram. 2.13.2 MAGNITUDE Displays the y-axis value of the cursor on the Histogram. 2.11 Retrieving Saved Data From a File The CDB5460A software allows the user to save data to a file, and retrieve it later when needed. To load a previously saved file: 1) Pull down the Setup option and select Disk. A file menu will appear. 18 2.13.3 MAXIMUM Indicator for the maximum value of the collected data set. DS487DB1 CDB5460A 2.13.4 MEAN Indicator for the mean of the data sample set. 2.14.6 S/PN Indicator for the Signal-to-Peak Noise Ratio (decibels). 2.13.5 MINIMUM Indicator for the minimum value of the collected data set. 2.14.7 # of AVG Displays the number of FFT's averaged in the current display. 2.13.6 STD. DEV. Indicator for the Standard Deviation of the collected data set. 2.15 Time Domain Information The following controls and indicators are associated with Time Domain Analysis. Time domain data can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to Time Domain (Figure 6). 2.13.7 VARIANCE Indicates the Variance for the current data set. 2.14 Frequency Domain Information The following describe the indicators associated with FFT (Fast Fourier Transform) Analysis. FFT data can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to FFT (Figure 7). 2.15.1 COUNT Displays current x-position of the cursor on the time domain display. 2.15.2 MAGNITUDE Displays current y-position of the cursor on the time domain display. 2.14.1 FREQUENCY Displays the x-axis value of the cursor on the FFT display. 2.15.3 MAXIMUM Indicator for the maximum value of the collected data set. 2.14.2 MAGNITUDE Displays the y-axis value of the cursor on the FFT display. 2.15.4 MINIMUM Indicator for the minimum value of the collected data set. 2.14.3 S/D Indicator for the Signal-to-Distortion Ratio, 4 harmonics are used in the calculations (decibels). 2.14.4 S/N+D Indicator for the Signal-to-Noise + Distortion Ratio (decibels). 2.14.5 SNR Indicator for the Signal-to-Noise Ratio, first 4 harmonics are not included (decibels). DS487DB1 19 20 TP34 J12 HDR2X2 HDR1 1 3 4 2 R17 VIN+ /EE_CS BNC_RA 301 0.1% C32 R12 4.99K /CS SDI D+ SCLK SDO VIN/CS SO /WP GND VCC /HOLD SCK SI 1 2 3 4 8 7 6 5 U9 D+ C2 4700PF COG .01UF COG TP35 J11 HDR2X2 HDR2 1 3 4 2 R18 C33 AT25040_10PC_2.7 GND BNC_RA 301 0.1% .01UF COG TP39 J10 HDR2X2 HDR8 1 2 R25 IIN+ 3 4 BNC_RA 301 0.1% C34 .01UF COG TP40 HDR2X2 HDR9 1 2 C3 4700PF COG J9 R26 IIN3 4 BNC_RA 301 0.1% C35 .01UF COG GND GND U10 XOUT CPUCLK D+ SCLK SDO /CS PFMON IIN+ IINVA+ AXIN SDI /EDIR /EOUT /INT /RESET GND VIN+ VINVREFOUT VREFIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SKT_SO24_ENP U3 D+ XOUT C15 .1UF CPUCLK C30 10UF XIN SDI /EDIR /EOUT /INT /RESET PFMON IIN+ IINVA+ GND SCLK SDO /CS MODE VIN+ VINVREFOUT VREFIN TP135 TP137 TP139 TP141 TP143 TP145 TP147 TP149 TP151 TP153 TP155 TP157 TP134 TP136 TP138 TP140 TP142 TP144 TP146 TP148 TP150 TP152 TP154 TP156 1 2 3 4 5 6 7 8 9 10 11 12 XIN XOUT SDI CPUCLK VD+ /EDIR /EOUT DGND SCLK /INT SDO /RESET /CS NC MODE PFMON VIN+ IIN+ VINIINVREFOUT VA+ VREFIN VACS5460_BS 24 23 22 21 20 19 18 17 16 15 14 13 TP111 TP113 TP115 TP117 TP119 TP121 TP123 TP125 TP127 TP129 TP131 TP133 TP110 TP112 TP114 TP116 TP118 TP120 TP122 TP124 TP126 TP128 TP130 TP132 C14 .1UF C29 10UF A- VA+ XIN 4.0960MHZ HDR2X2 HDR10 1 3 4 2 R19 12K CPUCLK XTAL1 JP2 XOUT PFMON GND Y2 C38 10PF COG GND GND C39 10PF COG U/CS USDI USDO USCLK U/INT U/EDIR U/EOUT U/RESET HDR11X2 HDR6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 /CS SDI SDO SCLK MODE_SEL U/EE_WR EE_WR MODE R28 15K AGND CDB5460A DS487DB1 Figure 9. Analog Schematic Part 1 VA+ 2 U4 LT1019CN8_2P5 IN GND TRIM HTR TEMP R30 10K R31 10K HDR3X2 HDR4 1 2 4 6 3 GND 4.99K R38 4.99K R36 VCC VCC /CS ISDI EE_WR ISDO MODE SCLK /EE_WR SDI 20 .1UF 10K 14 .1UF O0 O1 O2 O3 8 3 6 11 MODE_SEL U/CS USDI USCLK UEE_WR 1 2 4 6 8 1/G 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 18 16 14 12 1 2 4 5 13 12 10 9 USDI SDO SDI /EE_CS U/RESET MODE_SEL USDO U/EE_WR R34 /A0 B0 /A1 B1 /A2 B2 /A3 B3 19 11 13 15 17 2/G 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 /RESET MODE ISDO /EE_WR 9 7 5 3 10 GND 74VHC125N 7 GND SN74VHC244N GND VDDD GND GND GND VCC 1/G 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 20 C41 .1UF U8 HDR12 1 2 18 16 14 12 JP1 UXTAL1 U/INT U/EDIR U/EOUT USDO HDR1X2 XTAL1 /INT /EDIR /EOUT UEE_WR SDO 1 2 4 6 8 19 11 13 15 17 2/G 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 GND SN74HCT244N 9 7 5 3 10 U2 SN74HC00N U/EE_WR 12 13 11 GND UEE_WR DS487DB1 OUT 5 7 3 6 R24 49.9 C16 .1UF C20 .1UF A4 AA- J2 1 2 A- REF+ VREFOUT 5 R21 VREFIN 301 0.1% C1 .1UF C40 .1UF A- TERM_BLOCK AAD+ D+ A- C22 D+ D+ C37 U11 U12 GND GND CDB5460A Figure 10. Analog Schematic Part 2 21 LED_RED D3 1K HDR1X2 HDR11 1 2 1K R33 R32 U/EOUT U/EDIR R35 R10 R11 5.11K 5.11K 5.11K 22 20.000 MHZ Y1 UXTAL1 VDDD LED_RED D5 C24 33PF COG VDDD C23 33PF COG C7 47UF TP14 29 VDDD C17 .1UF BYPASS CAP 19 TP22 18 C19 .1UF GND GND UM1 8751-8 XTAL1 PSEN 30 D4 1N4148 GND TP15 NRST GND 31 14 XTAL2 EA 3 9 # 8-BIT MICRO 8751 ALE PROG 39 GND U2 VCC 1 2 ALE VDDD R9 RST R4 U/CS 750K SN74HC00N GND 200 TP33 7 1 C18 1.0 2 3 4 5 6 7 8 38 37 36 .1UF P0.0 R7 GND USDI TP38 TP23 TP24 TP29 P0.0 P0.1 P0.2 P0.3 200 TP32 TP31 TP30 R8 USDO 200 200 PORT1 200 TP11 TP10 TP9 GND R13 RESET R16 U/EE_WR USCLK R29 4.99K VDDD U/RESET 200 R37 GND TP8 S1 HDR13 1 2 PORT0 AD 35 34 33 32 TP28 TP27 TP26 P0.4 P0.5 P0.6 HDR1X2 S2 SW_B3W_1100 MODE_SEL 1.7 P0.7 21 TP25 P0.7 P2.0 22 23 24 TP69 TP1 TP2 TP3 P2.0 P2.1 P2.2 P2.3 OPEN SW_DIP_3 3 2 1 PORT2 A 25 26 27 28 TP4 TP5 TP6 P2.4 P2.5 P2.6 GND GND GND P2.7 D2 1 2 3 4 6 5 7 8 10 TP7 P2.7 P3.0/RXD 11 TP43 HDR2X2 HDR7 2 1 FROM RS-232 P3.1/TXD 12 TP42 4 3 TO RS-232 P3.2/\INT0 13 TP16 P3.2 P3.3/\INT1 14 TP17 R1 P3.4/T0 15 TP18 200 R2 P3.5/T1 TP19 16 U/INT 200 R3 P3.6/\WR 17 TP20 U/EDIR 200 U/EOUT P3.6 LED_555_5003 P3.7/\RD TP21 P3.7 CDB5460A DS487DB1 Figure 11. Digital Schematic Part 1 U6 VDDD P3.6 P2.5 P2.0 P2.1 P2.3 P3.7 P2.2 DS487DB1 C43 .1UF P2.6 P2.4 A7 A6 A5 A4 A3 A2 A1 A0 P0.0 P0.1 P0.2 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VCC /W A13 A8 A9 A11 /G A10 /E DQ7 DQ6 DQ5 DQ4 DQ3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND P0.7 P0.6 P0.5 P0.4 P0.3 U5 MCM6206DP20 1 11 ALE 3 4 7 8 13 14 17 18 /OC C GND P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 1D 2D 3D 4D 5D 6D 7D 8D A0 A1 A2 A3 A4 A5 A6 A7 VDDD 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q VCC GND 20 10 2 5 6 9 12 15 16 19 GND SN74HC373N SN74HC00N P2.7 8 9 10 C42 .1UF U2 P2.6 4 5 U2 SN74HC00N 6 CSUSB GND VDDD U1 20 C1+ C2+ GND C2VSS RX1 TX1 DO2 13 12 11 DI2 DO3 DI3 RX2 TX2 RX3 TX3 2 3 4 5 6 DI1 7 8 9 10 19 VCC C1VDD DO1 18 1 C26 10UF 10K 17 TP71 TP72 14 15 16 C25 10UF R14 C27 10UF C28 10UF TP12 TP13 FROM-PC TO-PC GND GND FROM RS-232 TO RS-232 5 9 4 8 3 7 2 6 1 J8 DE9F_RA MC145407P CDB5460A Figure 12. Digital Schematic Part 2 23 24 VACON_BANANA HDR2X2 HDR3 1 2 4 A- 3 J3 Z1 P6KE6V8P 47UF C5 .1UF C10 GND AGND CON_BANANA GND GND GND J6 GND Vu+ CON_BANANA J4 Z2 P6KE6V8P C6 47UF C12 .1UF GND GND GND VD+ CON_BANANA J13 Z4 P6KE6V8P C11 47UF C21 .1UF GND VA+ CON_BANANA HDR4X2 HDR5 1 2 3 4 VA+ VDDD R15 10 C13 .1UF C8 47UF J5 L2 FERRITE_BEAD 5 7 6 8 D+ Z3 P6KE6V8P GND GND GND CDB5460A DS487DB1 Figure 13. Power Supply Schematic DS487DB1 CDB5460A Figure 14. Silkscreen 25 26 CDB5460A DS487DB1 Figure 15. Circuit Side DS487DB1 CDB5460A Figure 16. Solder Side 27 CDB5460A 3. ADDENDUM 3.1 Board Modifications for Charge Pump The CDB5460A can be modified by the user, to include a charge pump circuit, whose output could be used to supply the VA- supply pin in the +2.5V and -2.5V analog power configuration. The diagram below illustrates the schematic of such a circuit. The components must be added by the user. 1) Header H1 allows a clock source to be clipped across J1 with J2 open to analyze the charge pump by itself or drive it asynchronous to the CS5460A. With J1 open and J2 closed, the pump is clocked synchronously with the CS5460A. For best results, the charge pump should be clocked synchronously with the CS5460A. 2) The charge pump is constructed from components C1, C2, D1 and D2. D1 and D2 are BAT85 schottky diodes chosen for their speed and low forward voltage. Capacitor C1 provides the necessary current at 4.096 MHz. Capacitor C2 provides extra storage if the load on A- is increased. If the external reference is removed (and therefore the CS5460A is the only load on A-) C2 can be removed. The bypass capacitors from VA+ to A- will be sufficient. 3) Header H2 connects the charge pump to A-. H2 can be removed to analyze the unloaded performance of the charge pump. This should be closed for "charge-pump" mode operation. 4) A four-pin socket (U1) is added to connect an optional clock oscillator to the XIN pin and easily operate the CS5460A in "external clock" mode. H1 HDR J1 C1 1.0 nF D2 BAT 85 H2 HDR A- J2 AGND D1 BAT 85 C2 1.0 nF AGND XIN CS5460 DGND XINT HDR 10 DGND AGND D+ CLOCK MC Already Exists Figure 17. CDB5460A Modifications for A- Charge Pump 28 DS487DB1 * Notes * |
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